Controlling two monitors with transmission of display data using a fifo buffer

ABSTRACT

A method for controlling two monitors on the basis of an input-side pixel data stream, in which one part of each line of the input-side pixel data stream is displayed on one of the monitors and another part of the line is displayed on another of the monitors, comprises the storing of one part of the line of the input-side pixel data stream in one FIFO memory device and the storing of the other part of the line of the input-side pixel data stream in another FIFO memory device. The readout of one FIFO memory device takes place with the pixel frequency with which one monitor is operated while the readout of the other FIFO memory device takes place with the pixel frequency with which the other monitor is operated. Thus, a moderately priced and high speed monitor control circuit is realized.

FIELD OF THE INVENTION

The present invention relates to interfaces between monitors andcomputers and in particular to the controlling of two monitors on thebasis of a pixel data stream.

DESCRIPTION OF BACKGROUND ART

The widespread use of window systems in personal computers andworkstations has resulted in a demand for larger monitors so as to beable to represent more windows on a monitor. Although more than 14-inchmonitors have become increasingly common recently, this option isexceedingly expensive, since even a relatively small enlargement of themonitor area leads to a considerable increase in the cost of themonitor. A user of window systems requires e.g. for simultaneous workingin a text processing system and e.g. in a graphics program or a CADprogram several windows on a screen. Because of the size of a screen itis nearly impossible to represent all the necessary windowssimultaneously and e.g. to activate one or other of the windows by meansof a keyboard or a mouse. The user is thus forced to close some windowsand open others when he wishes to change from one application toanother. In applications requiring a frequent back and forth between thevarious windows which represent different applications, the perpetualclosing and opening is a tiresome activity, which, for one thing,markedly reduces the user's working efficiency.

For this reason the need arose to connect two or more screens to apersonal computer or a workstation and to place them next to each otherso as to effectively double the effective line width through the use oftwo monitors. As a result a user is able e.g. to assign Windows controlwindows to one monitor, while an application, such as e.g. a textprocessing, is represented on the other monitor. If a user wants toincorporate graphic images in a text processing, a system with twomonitors enables him to perform a text processing on one monitor whileon the second monitor a graphic image is manipulated and dimensioned soas to fit into the place reserved for it in a document which is beingworked on. The same also applies e.g. to CAD applications, where thereis a desire for a high-quality, high-resolution screen for the CADapplication, whereas the control symbols on the other screen do notrequire the use of such a high-quality screen, thus enabling a saving inworking place costs.

In order to control two or more monitors from a computer so as to doubleor more than double the effective line width, it is necessary to“distribute” the graphic data generated by the computer correctly to theindividual screens. Among the devices for storing data to be representedon monitors are the so-called video random access memories or VRAMS, inwhich the data for display are addressed linewise. A line of a videorandom access memory can thus contain as many pixels as can berepresented in one line on an assigned monitor, this line only having tobe addressed with one address, however, as is known to persons skilledin the art.

In a known system for controlling two monitors, each monitor is equippedwith its own digital-analog converter, which is needed to convert thedigital data delivered by the computer into analog data required by themonitor. Furthermore, each digital-analog converter is connected to itsown video random access memory, which is in turn controlled by its owngraphics control. In a known system the data for display delivered by acomputer are passed over a host bus to a buffer, undergoing asoftware-implemented image division on the way. The host CPU, i.e. thecentral processing unit of the host system, stores the data to berepresented on the two monitors in video random access memories, one foreach of the monitors, from which, by means of the graphics controlprovided for each video random access memory, data can be read out andconverted into an analog form for display on the monitors. The knownsystem thus comprises two parallel branches, a branch consisting of amonitor, a digital-analog converter, a video random access memory and agraphics control, the two branches being connected and controlled by asoftware image division unit, which is fed by the host bus of thecomputer via a data buffer, which may likewise be implemented as a VRAM.The host CPU must thus undertake the division of the pixel stream inthis known system. The pixel stream to be represented on the monitorsmust thus be apportioned to the respective video random access memoriesby the software image division unit.

A disadvantage of the known system is that a separate video randomaccess memory and a separate graphics control must be provided for eachmonitor, which means that a system of two monitors and a computer isunnecessarily costly. Furthermore, the software-implemented imagedivision in the software image division unit is slow, meaning that theimage buildup times of the system of two monitors are increasedunnecessarily.

SUMMARY OF THE INVENTION

Starting from this prior art, it is the object of the present inventionto provide an economic and fast way of controlling two monitors on thebasis of an input-side pixel data stream.

In accordance with a first aspect of the present invention, this objectis achieved by a method for controlling two monitors on the basis of aninput-side pixel data stream, in which pixels for a line are arrangedserially, wherein one part of each line of the input-side pixel datastream is displayed on one monitor and another part of the line isdisplayed on another monitor, comprising the steps of storing one partof the line of the input-side pixel data stream in one FIFO memorydevice without previous buffering; subsequent to the storing of thefirst part, storing the other part of the line of the input-side pixeldata stream in another FIFO memory device without previous buffering;reading out one FIFO memory device with the pixel frequency with whichone monitor is operated; and reading out the other FIFO memory devicewith the pixel frequency with which the other monitor is operated.

In accordance with a second aspect of the present invention, this objectis achieved by a monitor control circuit for controlling two monitors onthe basis of an input-side pixel data stream, in which pixels for a lineare arranged serially, wherein one part of each line of the input-sidepixel data stream is displayed on one monitor and another part of theline of the input-side pixel data stream is displayed on anothermonitor, comprising two FIFO memory devices; and a control device forcontrolling the storage of one part of the line of the input-side pixeldata stream in one FIFO memory device without previous buffering, forcontrolling the storage of the other part of the line of the input-sidepixel data stream in the other FIFO memory device without previousbuffering and subsequent to the storing of the first part, forcontrolling the readout of one FIFO memory device with the pixelfrequency with which one monitor is operated, and for controlling thereadout of the other FIFO memory device with the pixel frequency withwhich the other monitor is operated.

The invention is based on the finding that it is possible to dispensewith a separate video random access memory for each monitor by replacingeach video random access memory with a fast and cheap FIFO memory deviceand FIFO control logic units circuited between two FIFOs. The operationof the FIFO memory devices for each monitor is controlled andsynchronized through respective FIFO control logic units circuitedbetween two FIFOs. In a preferred embodiment which employs VRAMS, theFIFO memory devices for each monitor are fed from a single VRAM framebuffer (i.e. image memory), which is in turn controlled by a graphicscontrol. As a result only one frame buffer and one graphics control areneeded to control all the monitors connected to a computer.

BRIEF DESCRIPTION OF THE DRAWINGS

A preferred embodiment of the present invention will be described inmore detail below making reference to the enclosed drawings, in which:

FIG. 1 shows an overview of a computer system with two monitorsaccording to the present invention;

FIG. 2 shows a block diagram according to an embodiment of the presentinvention; and

FIG. 3 shows a timing diagram for the block diagram from FIG. 2.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

FIG. 1 shows an overview of a computer system for controlling twomonitors 10 a, 10 b. In the preferred embodiment of the presentinvention which is shown in broad outline in FIG. 1 only two monitors 10a and 10 b are controlled. However, from the description of the presentinvention it will be obvious to persons skilled in the art that aplurality of monitors which include the monitor 10 a and the othermonitor 10 b can also be controlled. Each of the monitors 10 a and 10 bhas a digital-analog converter, 12 a and 12 b respectively, assigned toit. The digital-analog converters 12 a and 12 b may either be integratedin the respective monitor, which is not customary, however, or they maybe located externally, e.g. on a graphics card. The inputs to thedigital-analog converters 12 a and 12 b are digital signals 14 a and 14b respectively and in a preferred embodiment of the present inventionthey supply analog RGB signals 16 a, 16 b.

The digital-analog converter 12 a is supplied from a first FIFO memorydevice 18 a with pixel data to be represented on the monitor 1 a, saidpixel data forming part of the digital input signals 14 a for thedigital-analog converter 12 a. In analogous fashion to this a secondFIFO memory device 18 b feeds the digital-analog converter 12 b withdigital pixel data to be displayed on the monitor 10 b. The first andthe second FIFO memory devices are supplied with pixel data from aninput-side pixel data stream 20, said pixel data being fetched from aframe buffer 22, which in a preferred embodiment is a video randomaccess memory (VRAM). A graphics control 24 receives the pixel datastream 20 created on the input side, together with timing controlsignals for the same, from a host bus 26, which is connected to acomputer. It should be pointed out here that the overview in FIG. 1shows only the apportioning of the input-side pixel data stream to thetwo monitors 10 a and 10 b, whereas no control signals are shown in FIG.1.

As has already been mentioned, in a preferred embodiment of the presentinvention VRAMs are used, which constitute the frame buffer 22. In otherpreferred embodiments of the present invention in which DRAMs, SDRAMS,SGRAMS or WRAMs are used, the frame buffer 22 is not necessary since aninput-side pixel data stream 20 can then be generated in the graphicscontrol and fed directly into the two FIFO memory devices 18 a, 18 b, asis shown by the dashed line in FIG. 1. In the sense of the presentinvention it is thus possible to say that the input-side pixel datastream 20 is present at the inputs of the two FIFO memory devices 18 a,18 b, said pixel data stream being apportioned accordingly to the firstand the second monitors 10 a and 10 b. Correct apportioning of the pixeldata stream 20 is controlled by a FIFO control logic 28, which isdescribed in more detail in FIG. 2. The FIFO control logic 28 alsosupports the correct readout of the FIFO memory devices 18 a and 18 b.

FIG. 2 shows a detailed block diagram of the overview in FIG. 1. Theinput-side pixel data stream 20 or 20′ from the frame buffer 22 or fromthe graphics control 24 respectively is present both at the first andthe second FIFO memory device. Both FIFO memory devices 18 a and 18 bhave three inputs, WRITE ENABLE for a write enable signal, WRITE CLK fora write clock signal and DATA IN for the input-side pixel data stream.On the output side the first FIFO memory device and the second FIFOmemory device have an output READ ENABLE for a read enable signal, anoutput READ CLK for a read clock signal and an output DATA OUT for thedigital pixel signals 14 a and 14 b into the digital-analog converters12 a and 12 b respectively. As has already been described in FIG. 1, thefirst FIFO memory device 18 a is followed by the digital-analogconverter 12 a, which supplies the monitor 10 a. In the same way thesecond FIFO memory device 18 b is followed by the digital-analogconverter 12 b, which in turn supplies the other monitor 10 b.

The first and the second FIFO memory devices 18 a, 18 b are controlledby a control 30, which encompasses a time generator 32, a frequencysetting device 34 and also the FIFO control logic 28 already referred toin FIG. 1. The FIFO control logic 28 comprises a screen resolutionregister 36, a pixel counter 38 and a programmable delay unit 40. Thescreen resolution register 36 is in contact with the host bus 26 (FIG.1), from which the screen resolution register receives specific data forthe monitors 10 a and 10 b via an address input ADDRESS and via a datainput DATA. These monitor-specific data comprise the complete lineresolution of both monitors, i.e. the number of pixels in a line of onemonitor 10 a added to the number of pixels of a line of the othermonitor 10 b. In a preferred embodiment of the present invention thenumber of pixels of a line of one monitor 10 a is the same as the numberof pixels of a line of the other monitor 10 b. A line of the input-sidepixel data stream 20 thus has twice as many pixels as a line of amonitor 10 a or 10 b. One part of a line of the input-side pixel datastream 20 is consequently represented on the monitor 10 a while theother part of the line of the input-side pixel data stream isrepresented on the other monitor 10 b. In the embodiment described thetwo parts are of the same size and the two parts together constitute aline of the input-side pixel data stream 20. The present invention isalso applicable to systems with more than two monitors, however, andalso to systems in which the partial lines represented on monitors havea different number of pixels. Information on the number of monitors andon the number of pixels of a line of each monitor resides in the screenresolution register 36. As the preferred embodiment of the presentinvention features two monitors 10 a and 10 b having the same lineresolution, a resolution signal is output via an output RES/2 with avalue corresponding to half the resolution of the input-side pixel datastream 20, i.e. to the full resolution of the monitor 10 a or 10 b. Theresolution signal is supplied to the pixel counter 38 as counterreference signal via an input COUNT REF. The pixel counter 38 also hasinputs BLANK and CLK for a blanking signal and a clock signalrespectively. On the output side the pixel counter 38 has two outputsWRENFIFO 1 and WRENFIFO 2 for sending a write enable signal to the firstFIFO memory device 18 a and a write enable signal to the second FIFOmemory device 18 b respectively. The programmable delay unit 40 has aninput HSYNC for a horizontal synchronization signal, an input BLANK fora blanking signal, an input CLK for a clock signal and an input DELAYVALUE for a delay value signal from the screen resolution register 36.On the output side the programmable delay unit 40 has an output DELAYEDHSYNC for a delayed horizontal synchronization signal and an outputDELAYED BLANK for a delayed blanking signal.

The vertical synchronization signal, the blanking signal and the clocksignal are created in a time generator 32, which is capable ofextracting the control signals from the data stream which is transmittedfrom the host bus 26 to the graphics control 24 and which contains boththe input-side pixel data stream 20 and control signals for the same.The time generator 32 can thus be an external unit or it can beintegrated in the graphics control 24. In the preferred embodiment ofthe present invention the frequency setting device 34, which likewiseforms part of the control 30, performs a divider function in order tocreate from the clock signal CLK a clock signal with half the frequencyof the clock signal CLK, the frequency of the halved clock signal CLK/2corresponding to the operating frequency of the monitors 10 a and 10 b.

The two digital-analog converters 12 a, 12 b are equipped, in a mannerknown to persons skilled in the art, with inputs VSYNC for the verticalsynchronization signal, HSYNC for the horizontal synchronization signal,BLANK for the blanking signal, LOAD CLK for a load clock signal and aninput PIX DATA for the pixel data to be converted to an analog form. Onthe output side the digital-analog converters 12 a and 12 b have anoutput RGB OUT for providing the respective input RGB IN of the monitors10 a and 10 b with an RGB signal, as is known to persons skilled in theart.

The functioning of the block diagram shown in FIG. 2 and described abovewill now be described making reference to FIG. 3. The clock signal CLKcan have a clock frequency which conforms to any standard. In FIG. 3 atiming diagram for an active display time 42 of eight pixels isdescribed. For persons skilled in the art it is obvious that theprinciple is applicable to all other display times, the restriction toan active display time of eight clock periods or eight pixels servingsolely to clarify and simplify matters.

The input-side pixel data stream 20 thus has a line length of 8 pixels,the two monitors 10 a and 10 b each having a line width of four pixels.A line of the input-side pixel data stream is thus divided into one partwith a length of four pixels and another part with the same length offour pixels.

The blanking signal BLANK is known to persons skilled in the art and inits logical high state it activates the digital-analog converter 12 a,which is assigned to the monitor 10 a. The blanking signal BLANK thusdefines the active display time 42, there being a pause of 2 periods ofthe clock signal CLK, in which the known horizontal synchronizationsignal HSYNC goes into the high state for the duration of one clockperiod, between a first displayed line and a second displayed line 46.The signal WRENFIFO1 makes it possible to write into the first FIFOmemory device 18 a for a part 48 of a line of the input-side pixel datastream 20, while the write enable signal for the second FIFO memorydevice WRENFIFO2 enables the second FIFO memory device 18 b for anotherpart 50 of a line of the input-side pixel data stream 20. The effect ofthe phase displacement of the two signals WRENFIFO1 and WRENFIFO2 by180° is that the first four pixels of a line of the input-side pixeldata stream 20 are clocked into the first FIFO memory device 18 a andthe next four pixels, i.e. the pixels 5 to 8, are clocked into thesecond FIFO memory device 18 b. The clock speed for writing into theFIFO memory devices 18 a and 18 b corresponds to the frequency of theclock signal CLK, it being important to note at this point that thesystem according to the present invention does not require a buffer ofany kind and that the FIFO memory devices 18 a and 18 b serve toapportion the input-side pixel data stream to the available monitors.

The write enable signals for the two FIFO memory devices 18 a and 18 bare created by the pixel counter 38, which may be a binary counter,which is set to a value of 4 by a counter reference signal at its inputCOUNT REF and which, during the time period following a rising flank ofthe blanking signal BLANK, outputs the signal WRENFIFO1 and which,during its second counting period after a rising flank of the blankingsignal BLANK, creates the signal WRENFIFO2.

As has already been mentioned, buffering does not occur, which is whythe two FIFO memory devices 18 a and 18 b are read from with half theclock frequency, generated in the frequency setting device 34, withwhich the pixels now distributed to the two monitors arrive in theirdigital-analog converters 12 a, 12 b. Alternatively, a small number ofclock periods may elapse before the read data are valid.

An example will now be considered in which a line consists of eightpixels, of which four pixels are to be sent for display to the monitor10 a and the other four pixels are to be sent for display to the monitor10 b. As may be seen from the last two lines of FIG. 3, the readoutoccurs in such a way that at the same time as the first pixel of a lineis being read out of the first FIFO memory device 18 a the last pixel ofthe previous line can be read out of the second FIFO memory device 18 b.When the second pixel of a line is being read out of the first FIFOmemory device 18 a, the other monitor 10 b is blanked, whereas when thethird pixel of a line is being read out of the first FIFO memory device18 a, the fifth pixel of the same line is read out of the FIFO memorydevice 18 b. Readout of the fourth pixel of a line from the first FIFOmemory device 18 a takes place simultaneously with the readout of thesixth pixel of the line of the input-side pixel data stream 20 from thesecond FIFO memory device 18 b. During readout of the seventh pixel ofthe line from the second FIFO memory device 18 b, no pixel is read outof the first FIFO memory device 18 a, in order to blank the monitor 10a. The blanking of the monitor 10 a is controlled by the horizontalsynchronization signal HSYNC and by the blanking signal BLANK, while theblanking of the other monitor 10 b is controlled by the delayedhorizontal synchronization signal DELAYED HSYNC and by the delayedblanking signal DELAYED BLANK. Both delayed signals are each delayed byhalf 52 the active display time 42 relative to their undelayed signals.

From the above example of a line with eight pixels it is clear how thereadout occurs for lines having more than eight pixels. It should benoted, however, that in a preferred embodiment of the present inventionthe FIFO 18 b is not read out until one half of a line for display hasbeen stored in the FIFO 18 a.

By providing FIFO memory devices which are deeper than four pixels, itis in principle possible to set the time shift between the readouts fromthe two FIFO memory devices 18 a and 18 b to any value; however, thesituation which has been described represents the most economical onesince it is not possible to read out pixel 5 of a line of the input-sidepixel data stream 20 prior to this occurring in parallel to the readoutof pixel 3 of the same line since it is not, as can be seen from thetiming diagram in FIG. 3, available beforehand.

1. A method for controlling two monitors on the basis of an input-sidepixel data stream, in which pixels for a line are arranged serially,wherein one part of each line of the input-side pixel data stream isdisplayed on one monitor and another part of the line is displayed onanother monitor, comprising the following steps: storing one part of theline of the input-side pixel data stream in one FIFO memory devicewithout previous buffering; subsequent to the storing of the first part,storing the other part of the line of the input-side pixel data streamin another FIFO memory device without previous buffering; reading outone FIFO memory device with the pixel frequency with which one monitoris operated; and reading out the other FIFO memory device with its pixelfrequency with which the other monitor is operated.
 2. A methodaccording to claim 1, with the following additional step: creatingtiming control signals for controlling the monitors on the basis oftiming control signals of the input-side pixel data stream.
 3. A methodaccording to claim 1, with the following additional step: delayingtiming control signals of the input-side pixel data stream, whereby oneof the monitors is controlled with a time delay and in synchronism withthe other monitor.
 4. A method according to claim 1, wherein one part ofeach line of the input-side pixel data stream and the other part of eachline of the input-side pixel data stream are of the same size andtogether have the length of a line of the input-side pixel data stream.5. A method according to claim 4, having the following additional steps:setting a counter reference value to the number of pixels of one part ofeach line of the input-side pixel data stream; and counting the pixelsof each line of the input-side pixel data stream by counting the pulsesof a clock with which the input-side pixel data stream is stored in eachof the FIFO memory devices.
 6. A method according to claim 5, with thefollowing additional steps: enabling the storage of one part of the lineof the input-side pixel data stream in one FIFO memory device andblocking storage in the other FIFO memory device before reaching thecounter reference value and after the appearance of a blanking signal;and enabling the storage of the other part of the line of the input-sidepixel data stream in one FIFO memory device and blocking storage in theother FIFO memory device after reaching the counter reference value andafter the appearance of the blanking signal.
 7. A method according toclaim 6, with the following additional steps: setting the pixelfrequency of each monitor to half the clock frequency; halving thefrequency of the clock signal; reading out one FIFO memory device withthe halved clock frequency on appearance of the blanking signal;delaying the blanking signal by a time which is equal to the number ofpixels of one part of the line of the input-side pixel data streammultiplied by the period duration of the clock signal; and reading outthe other FIFO memory device on appearance of the delayed blankingsignal in such a way that both FIFO memory devices are read out insynchronism and with a time shift.
 8. A method according to claim 4,with the following additional steps: detecting a horizontalsynchronization signal in the input-side pixel data stream; delaying thehorizontal synchronization signal by a time which is equal to the numberof pixels of one part of the line of the input-side pixel data streammultiplied by the period duration of the clock signal; and reading outthe other FIFO memory device after the appearance of the delayedhorizontal synchronization signal in such a way that both FIFO memorydevices are read out in synchronism and with a time shift.
 9. A methodaccording to claim 1, wherein the pixel frequency with which on monitoris operated and the pixel frequency with which the other monitor isoperated together amount to the clock frequency with which one part ofthe line of the input-side pixel data stream is stored in one FIFOmemory device and the other part of the line of the input-side pixeldata stream is stored in the second FIFO memory device.
 10. A monitorcontrol circuit for controlling two monitors on the basis of aninput-side pixel data stream, in which pixels for a line are arrangedserially, wherein one part of each line of the input-side pixel datastream is displayed on one monitor and another part of the line of theinput-side pixel data stream is displayed on another monitor,comprising: two FIFO memory devices; and a control device forcontrolling the storage of one part of the line of the input-side pixeldata stream in one FIFO memory device without previous buffering, forcontrolling the storage of the other part of the line of the input-sidepixel data stream in the other FIFO memory device without previousbuffering and subsequent to the storing of the first part, forcontrolling the readout of one FIFO memory device with the pixelfrequency with which one monitor is operated, and for controlling thereadout of the other FIFO memory device with the pixel frequency withwhich the other monitor is operated.
 11. A monitor control circuitaccording to claim 10, wherein the control includes a time generatorwhich creates timing control signals for controlling the monitors on thebasis of timing control signals of the input-side pixel data stream andwhich is also connected to a frequency setting device for setting thepixel frequencies with which the monitors are operated so as to takeaccount of the pixel frequency of the input-side pixel data stream. 12.A monitor control circuit according to claim 11, wherein the controlalso includes a FIFO control logic, the FIFO control logic comprising: ascreen resolution register, which can be connected to a host bus of acomputer and which supplies length values of one part and of the otherpart of the line of the input-side pixel data stream in response tocontrol signals from the computer; a pixel counter, which can beconnected to the time generator and which creates FIFO control signalsfor controlling the two FIFO memory devices on the basis of the timingcontrol signals of the input-side pixel data stream; and a programmabledelay unit, which creates delayed control signals for controlling one ofthe monitors on the basis of timing control signals and on the basis ofthe lengths of the two parts of the line of the input-side pixel datastream.